In conventional VLSI systems memory testing is done in three essential steps. In the first step, hardwired logic employs algorithms developed before the device is committed to tape-out. These are often available through third-party vendors, examples are memBIST, MSIST. Deciding on the detailed make-up of hardwired logic is not feasible because it is impossible to predict the necessary information derived from process model during the process qualification window. In the second step, conventional memory testing attempts to close testing gaps using central processing unit (CPU) based approaches. These have a number of limitations. The major limitation is that there may be memory functions largely inaccessible via a CPU interface. Another severe limitation is the inability to do back-to-back accesses to all memories. The third step uses DMA external memory accesses while the device is in wafer form. Such DMA external memory accesses cannot be accomplished at full processor speed. Thus a significant number of failures are not observable.
FIG. 1 illustrates a conventional memory built-in-self-test (BIST) block diagram. The core functions are: (1) the BIST controller state machine 101 made up of hard-wired logic; and (2) the BIST data logger 102. The BIST controller 101 communicates with the BIST data logger 102 via bus 115 and supplies stimulus to multiple RAMs under test 103 via multiple buses 110. BIST data logger 102 accumulates the test results via multiple buses 111 and passes them to an external interface via bus 113. BIST data logger 102 compares expected results 114 received via bus 112 with return read data from the multiple RAMs 103 received via bus 111.
Major difficulties with conventional BIST memory test systems include:
1. Test algorithms must be hard wired into the BIST controller state machine 101;
2. Multiple RAMS must be driven with stimulus and results must be extracted from these multiple RAMs requiring complex interconnect paths;
3. Back-to-back memory access to all memories are not feasible; and
4. Memories cannot be tested at speed while in wafer form.
These and other problems with the prior art provide a need for a new kind of memory testing.